This application claims the benefit of German patent application DE10113458.4, currently pending, which is incorporated herein by reference in its entirety.
The invention relates to a test circuit for testing a circuit clocked with a high-frequency clock signal, in particular a high-frequency DRAM memory.
DE 198 23 931 A1 discloses a test pattern generator circuit for an IC tester. In the test pattern generator circuit, pattern data from a pattern memory are applied in parallel form to a parallel/serial converter. The parallel/serial converter can be changed over, on the basis of a mode control signal, between a serial output mode, in which the data for a data word are provided in serial form for each test cycle, and a parallel/serial output mode, in which parallel data are provided in serial form during each test cycle.
FIG. 1 shows a test arrangement based on the prior art. In this case, a circuit to be tested (DUT: Device Under Test) is tested by a tester when the manufacturing process is complete. The circuit to be tested is a synchronous semiconductor circuit clocked with a clock signal, for example a DRAM memory. The circuit to be tested is connected to the tester via a control signal bus, a data bus and an address bus. The tester uses the control signal bus to apply various control signals to the circuit to be tested. If the circuit to be tested is a DRAM memory, control lines are used to apply, inter alia, the control signals CAS (CAS: Column Address Strobe), RAS (RAS: Row Address Strobe), WE (WE: Write Enable) and CS (CS: Chip Select). The CAS signal indicates to the memory to be tested that the address which is on the address bus is a column address, while the RAS control signal indicates to the memory that the address which is on the address bus is a row address. Using the CAS control signal and the RAS control signal allows an address bus with a relatively narrow address bus width to be used. The CS control signal selects the memory which is to be tested from a multiplicity of available memories.
The clock frequencies at which modern memories are operated are becoming higher and higher, and already DRAM memories are being manufactured which operate at a clock frequency of several hundred megahertz. The drawback of the test arrangement shown in FIG. 1 is that conventional testers are not designed for such high clock frequencies. Testers suitable for testing memory chips which are clocked at a very high clock frequency of several hundred megahertz are complex in terms of circuitry and are accordingly costly.
It is therefore the object of the present invention to provide a test circuit which makes it possible to test a circuit clocked with a high-frequency clock signal using a conventional tester which outputs control signals at a comparatively low clock frequency.
The invention achieves this object by means of a test circuit having the features specified in patent claim 1.
The invention provides a test circuit for testing a circuit clocked with a high-frequency clock signal, where the test circuit has:
(a) a frequency multiplication circuit which multiplies the clock frequency of a clock signal, output by the tester, for producing the high-frequency clock signal by a frequency multiplication factor;
(b) a control signal input bus for receiving various external control signals for the circuit which is to be tested from the tester,
where each control signal is received in parallel via a plurality of control lines whose number is respectively equal to the frequency multiplication factor;
(c) a parallel/serial converter which is clocked with the high-frequency clock signal, is connected to the control signal input bus and outputs each control signal to the circuit to be tested via a control line of a control signal output bus; and
(d) a decoder circuit which is clocked with the high-frequency clock signal and produces internal control signals for the test circuit on the basis of the control signals which are on the control signal input bus.
The inventive test circuit has the particular advantage that the internal control signals required for the various circuit components in the test circuit are produced from the external control signals output by the tester for testing the circuit and thus do not need to be provided via additional control lines from the tester. In this way, the bus width of the control signal input bus is determined solely by the number of control signals required for the circuit which is to be tested, and is not increased by additional control signal lines for internal control signals in the test circuit. The bus width of the control signal input bus is therefore minimal.
In one preferred embodiment of the inventive test circuit, the test circuit is provided with a test data pattern generator which, on the basis of data control signals received from the tester via data control lines, applies stored test data patterns to a data comparison circuit and, via a data output driver and a data bus, to the circuit which is to be tested.
The data comparison circuit in the inventive test circuit preferably compares the output test data, received by the test circuit via the data bus and a data input driver from the circuit which is to be tested, with the test data patterns applied to the circuit to be tested.
The data input driver and the data output driver in the inventive test circuit are preferably activated by an internal read/write control signal produced by the decoder circuit.
The data comparison circuit in the inventive test circuit preferably indicates to the tester via an indicator line whether the output test data which are output by the circuit to be tested are identical to the test patterns applied to the circuit to be tested.
In this case, the data comparison circuit is preferably clocked with the high-frequency clock signal.
In one particularly preferred embodiment, the frequency multiplication factor is four.
The high-frequency clock signal preferably has a clock frequency of 400 MHz.
In one particularly preferred embodiment of the inventive test circuit, the signal delay times on the control lines of the control signal output bus are much shorter than the signal delay times on the control lines of the control signal input bus.
In one preferred embodiment, the test circuit is integrated in the circuit to be tested.
The inventive test circuit is preferably used for testing a DRAM memory.
Preferred embodiments of the inventive test circuit are described below with reference to the appended figures in order to explain features which are fundamental to the invention.